School of Engineering \ Computer Engineering
Course Credit
ECTS Credit
Course Type
Instructional Language
Programs that can take the course
Performance analysis in computer systems, single-cycle and multi-cycle processor designs, instruction set architecture, programming in assembly language, types of instructions, pipeline structures, control issues in computer architecture and their possible solutions, branch predictors, cache and virtual memory structures, input/output in computer systems.
Textbook and / or References
David A. Patterson, John L. Hennesy, Computer Organisation and Design, Fourth Edition: The Hardware/Software Interface (The Morgan Kaufmann Series in Computer Architecture and Design) ISBN-13: 978-0123744937
Understanding the working principles of the basic components that make up a computer, identifying and solving potential problems that may occur in hardware design, performance criteria and methods for improving performance, and designing computer components using logic circuit elements and hardware description languages.
1. Identifying factors affecting performance, learning the concept of Cycles Per Instruction (CPI) and the relationship between performance and execution time.
2. Designing a single-cycle processor on paper and using hardware description languages according to given requirements and constraints, creating the control table. Learning general information about multi-cycle processors and performing performance calculations.
3. Calculating the performance achieved with given branch predictors on a piece of code containing control instructions and determining the branch predictor with the highest performance for this code.
4. Calculating the performance of a processor using pipelining and identifying problems.
5. Determining the cache and virtual memory performance of a given piece of code.
6. Implementing a specified input-output protocol on a given system.
Week 1: Performance
Week 2: Instruction Set Architecture
Week 3: Instruction Set Architecture
Week 4: Instruction Set Architecture
Week 5: Pipelining
Week 6: Pipelining
Week 7: Branch Predictors
Week 8: Cache
Week 9: Cache
Week 10: Cache
Week 11: Virtual Memory
Week 12: Input/Output
Tentative Assesment Methods
• Midterm 40 %
• Final 60 %
• Bonus Homework 15 %
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D
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D
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D
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